In the semiconductor industry, memory cells are among the most important integrated circuit devices and have been the source of continuing research. Continued developments have been undertaken in the industry to increase storage capacity, enhance charge-retaining capability, improve writing and reading speeds, and decrease device dimensions of memory cells. Many memory cells rely on capacitors as charge storage devices. For example, a dynamic random access memory (DRAM) cell generally includes a transistor and a capacitor controlled by the transistor. The capacitor is a single charge storage capacitor for storing a logical status. The transistor, which is commonly referred to as a pass transistor, controls the writing and reading of the logical status stored in the capacitor. The transistor may be a field-effect transistor (FET), and frequently, an N-channel field effect transistor (N-FET). To further illustrate the background of the related art without limiting the scope and application of the present invention, the following paragraphs describe the application of a capacitor in a DRAM.
Generally, a DRAM cell can be divided into three designs: planar, stacked-capacitor, and trench. In the planar design, the transistor and capacitor of a cell are produced as planar components. The planar design generally requires more area per memory cell than the other two designs because the capacitor and transistor occupy separate areas of a semiconductor substrate. In the stacked-capacitor design, the capacitor of a cell is disposed above the transistor to reduce the substrate area occupied by each cell. Various designs for vertically extending the capacitor have been developed in recent years. In the trench design, the transistor is disposed on the surface of a substrate, and the capacitor is disposed in a trench formed in the substrate. The trench design allows the formation of densely arranged memory cell arrays.
Generally, trench capacitors provide comparatively large capacitance while occupying a comparatively small area on a semiconductor chip surface. Trench capacitors are characterized by deep and narrow trenches formed in the semiconductor substrate. An insulator or dielectric formed on the trench walls serves as the capacitor dielectric. Generally, two capacitor electrodes are formed with the capacitor dielectric being disposed between the two electrodes. The capacitance (C) of a trench capacitor is determined as follows:C=εA/d,
where ε is the permittivity of a capacitor dielectric, A is the surface area of the capacitor dielectric, which is disposed between the two electrodes, and d is the thickness of the capacitor dielectric. From the foregoing relationship, the capacitance of a trench capacitor may be increased by providing a capacitor dielectric with a high permittivity (ε), forming a trench capacitor having a large surface area of a capacitor dielectric (A), or using a thin capacitor dielectric.
Hemispherical silicon grain (HSG) has been used in stacked-capacitor DRAM cells to increase the surface area of the electrodes, which correspondingly increases the surface area of the dielectric. To integrate the HSG into trench capacitor DRAM cells, however, the HSG formed on the upper surfaces of the trenches must be removed for a number of reasons. The HSG formed on the upper surfaces of a trench further narrows an already narrow opening of the deep trench, which prevents electrode material, generally polysilicon, from fully filling the deep trench. The narrow trench opening therefore may create voids in the electrode to adversely affect the conductivity of the capacitor electrodes. In addition, an electrode having an overly narrow passage will likewise adversely affect the conductivity of the electrode. Furthermore, HSG may couple separate doped silicon substrate portions formed along one trench surface contiguous with an upper portion and lower portion of the deep trench to form an undesired parasitic transistor.
Removing HSG formed on the upper surfaces of the trench requires sacrificial layers, or sacrificial collars, to act as an etch stop to remove HSG without damaging the silicon substrate surface. However, conventional techniques of forming the sacrificial collars are complex and costly, one reason being the need to first provide the sacrificial layer, and then remove only the sacrificial layer formed on the mid- to lower-surfaces of the deep trench to maintain electrical connection between the doped silicon substrate portions contiguous with the lower surfaces of the deep trench and the subsequently-formed doped polysilicon provided in the deep trench.